1. Technical Field
The present invention relates to a vertical type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) to be used as a semiconductor device for electric power, which is preferable in the case of adoption as MOSIC and the like in which an elemental article thereof or the semiconductor device for electric power is incorporated.
2. Background Art
The vertical type power MOSFET has many features such that it has excellent frequency characteristics, has a fast switching velocity, can be driven at low electric power and the like, so that it has recently been used in many industrial fields. For example, in "Nikkei Electronics" published by Nikkei-McGraw-Hill, Inc. on May 19, 1986, pp. 165-188, it is described that the focus of development of the power MOSFET is in migrating to low voltage resistant articles and high voltage resistant articles. Further, it is described in this literature that the ON-resistance of a power MOSFET chip having a voltage resistance not more than 100 V has become low up to a level of 10 m.OMEGA., and it is described as a reason thereof that the channel width per area has been able to be made large by utilizing the fine processing of LSI in the production of the power MOSFET, or by improving the shape of its cell. In addition, in this literature, the description is made using the vertical type power MOSFET as a main topic in which a DMOS type (double diffusion type) cell which is in the main current is used. The reason is that the DMOS type is fabricated by the planar process characterized in that the flat main surface of a silicon wafer is exactly used for a channel portion, so that it has advantages in production of a good yield and a cheap cost.
On the other hand, in accordance with popularization of the vertical type power MOSFET, the realization of low loss and low cost is further demanded, however, the reduction in the ON-resistance by the fine processing or the improvement in the shape of the cell has arrived at the limit. For example, according to the official gazette of Japanese Patent Application Laid-open No. Sho 63-266882 (1988), it has been known that the DMOS type has a local minimum point in which the ON-resistance does not further decrease even when the size of the unit cell is made small by fine processing, and a major cause thereof is the increase in the JFET resistance which constitutes a component of the ON-resistance. In addition, with respect to the DMOS type, as shown in the official gazette of Japanese Patent Application Laid-open No. Hei 2-86136 (1990), the size of the unit cell with which the ON-resistance provides the local minimum point is in the vicinity of 15 .mu.m under the present fine processing technique.
In order to break through this limit, various structures have been proposed. The common feature among them is a structure in which a groove is formed on the device surface, and channel portions are formed at side faces of the groove, and owing to this structure, the above-mentioned JFET resistance can be greatly decreased. Further, in the structure in which the channel portions are formed at the side faces of the groove, the increase in the JFET resistance can be neglected even when the unit cell size is made small, so that there is no limit that the ON-resistance provides the local minimum point with respect to the reduction in the unit cell size as described in the official gazette of the Japanese Patent Application Laid-open No. Sho 63-266882 (1988), and it can be made small to the limit of the fine processing breaking though 15 .mu.m.
The structure, in which the channel portions are formed at the side faces of the groove, is called the R (Rectangular)-MOS device or the U (U-shaped)-MOS device according to its shape. The structure shown in the official gazette of Japanese Patent Application Laid-open No. Sho 59-8743 (1984) is an example of the R-MOS device, which is a structure alternatively called the trench gate type in which a vertical groove is formed at the device surface by means of the anisotropic dry etching method, and channels and a gate are formed at sidewall portions of this groove, and this can completely extinguish the JFET resistance component. On the other hand, the structure shown in the official gazette of Japanese Patent Application Laid-open No. Hei 2-86171 (1990) is an example of the U-MOS in which the anisotropic wet etching of silicon or the LOCOS oxidation (Local Oxidation of Silicon) method is used as a method for processing the channel portion into the U-groove shape, and this can also greatly reduce the JFET resistance component.
Typical conventional examples of the vertical type power MOSFET in which the channel portions are formed at the side faces of the groove are shown in FIG. 14 (R-MOS) and FIG. 15 (U-MOS).
At first, the R-MOS device shown in FIG. 14 will be explained. In this vertical type power MOSFET, at the surface layer porion of an epitaxial layer 2 comprising an n.sup.- -type layer provided on a main face of a semiconductor substrate 1 comprising an n.sup.+ -type silicon, a p-type diffusion layer and an n.sup.+ -type diffusion layer are successively formed by ion implantation and thermal diffusion. Next, in order to allow parts of these p-type diffusion layer and n.sup.+ -type diffusion layer to remain as a p-type base layer 16 and an n.sup.+ -type source layer 4 respectively, the reactive ion etching method is used to perform etching until penetration though the p-type diffusion layer in the vertical direction with respect to the silicon substrate is achieved, so as to form a trench groove 50. A gate oxide film 8 is formed on an inner wall 51 of this trench groove 50, on which a gate electrode 9 is formed. Thus channels 5 are formed at sidewall portions of the inner wall 51, and the channel length is determined by a thickness of the p-type base layer 16. The ohmic contact is made for a source electrode 19 with the n.sup.+ -type source layer 4, and for a drain electrode 20 with the back face of the semiconductor substrate 1, respectively.
In this R-MOS device, the ON-resistance between the drain and the source thereof is approximately the same as a sum of a channel resistance and a resistance of the n.sup.- -type drain layer 6, in which there is no JFET resistance which has been a problem in the above-mentioned DMOS type. Therefore, the ON-resistance monotonously decreases in accordance with the reduction in the unit cell size a", the reduction can be made up to 5 to 6 .mu.m which is the limit in the present fine processing, and the ON-resistance per area can be greatly reduced as compared with the DMOS type.
However, the R-MOS device has drawbacks in that the yield and the reliability are low. The cause is that the trench groove 50 is formed by the reactive ion etching method, and therefore the flatness of the sidewall surface of the inner wall 51 is bad and produces many defects, and the film quality of the gate oxide film 8, which is formed by oxidizing the surface thereof, is bad. Insulation inferiority of the gate oxide film, a decrease in the mobility due to the defect of the interface of the channel portion, and a change in the threshold voltage also take place. As described-above, the structure of the R-MOS device has the advantage of greatly reducing the ON-resistance per area, but there are problems of high cost resulting from the low yield, and a problem of difficulty to ensure the reliability due to the bad stability of the gate oxide film and the channel portion.
On the contrary, in the U-MOS device shown in FIG. 15, the anisotropic wet etching or the LOCOS oxidation method is used as the step for forming the U-groove instead of the reactive ion etching, so that the flatness of the sidewall surface is good, a U-groove 50 having an inner wall 51 with less defect can be formed, and so that the film quality of a gate oxide film 8 formed by oxidizing the surface thereof is also good. As a result, no insulation inferiority occurs, the characteristics of the channel portion can be made stable and the like, and a vertical type power MOSFET having a high yield and reliability can be obtained.
Fabrication steps for this U-MOS device will be explained in accordance with FIG. 16 to FIG. 19 and FIG. 15. In this vertical type power MOSFET, as shown in FIG. 16, using a mask of an insulation film 22 partially formed with a unit cell size a' of a cell on the main surface of a wafer 21 provided with an epitaxial layer 2 comprising an n.sup.- -type layer provided on a main face of a semiconductor substrate 1 comprising n.sup.+ -type silicon, boron is doubly diffused by selective ion implantation and thermal diffusion, so as to form a p-type diffusion layer 23 and a p.sup.+ -type contact region 17. Next, after removing the insulation film 22, as shown in FIG. 17, using a mask of an insulation film 24 partially formed on the main surface of the wafer 21, phosphorus is diffused so as to form an n.sup.+ -type diffusion layer 25 to overlap over p-type diffusion layers 23 of adjacent cells 15.
Next, after removing the insulation film 24, as shown in FIG. 18, using a mask of an insulation film 26 partially formed on the main surface of the wafer 21, the U-groove 50 is formed by the anisotropic etching or the LOCOS oxidation method. By the formation of this U-groove 50, peripheral edge portions of the adjacent p-type diffusion layers 23 and the central portion of the n.sup.+ -type diffusion layer 25 are removed, so as to form a p-type base layer 16 and an n.sup.+ -type source layer 4 separated by the U-groove 50 for every unit cell having a unit cell size of a'.
Next, after removing the insulation film 26, as shown in FIG. 19, a gate oxide film 8 is formed on the surface of the U-groove 50, and a gate electrode 9 comprising polysilicon is formed on this gate oxide film 8. Next, as shown in FIG. 15, an interlayer insulation film 18 is formed on the main surface of the wafer 21 so as to cover the gate oxide film 8 and the gate electrode 9, and the interlayer insulation film 18 is subjected to opening formation in order to expose parts of the p.sup.+ -type base contact layer 17 and the n.sup.+ -type source layer 4. A source electrode 19, which makes ohmic contact with the p.sup.+ -type base contact layer 17 and the n.sup.+ -type source layer 4, is formed on the main surface of the wafer 21. Further, a drain electrode 20 which makes ohmic contact with the back face of the semiconductor substrate 1 is formed, and the vertical type power MOSFET of the U-MOS structure is completed.
This U-MOS device shown in FIG. 15 has the feature that the yield and the reliability are high in a degree equivalent to the DMOS type, which is extremely excellent in this point as compared with the R-MOS device. This is due to the fact that the U-groove 50 is formed by the wet etching of silicon or the LOCOS oxidation method, thereby the flatness of its inner wall 51 is good with less defect, and the film quality of the gate oxide film 8 formed by oxidizing the surface thereof is also good, and it becomes difficult to cause the insulation inferiority of the gate oxide film and the characteristic change of the channel portion.
The ON-resistance between the drain and the source of the U-MOS is approximately the same as a sum of a channel resistance and a resistance of the n.sup.- -type drain layer 6 in the same manner as the above-mentioned R-MOS, and the JFET resistance of a JFET portion 7 is sufficiently small. Thus, in the same manner as in the above-mentioned R-MOS device, the ON-resistance decreases monotonously in accordance with the reduction in the unit cell size a', however, it can be only made slightly smaller than about 15 .mu.m of the DMOS type within the limit of the present fine processing, and cannot be made small into 5 to 6 .mu.m of the R-MOS type. However, since the JFET resistance is sufficiently small, the ON-resistance per area is an intermediate value between those of the R-MOS type and the DMOS type. As described above, the U-MOS has such a structure in which the feature of the low ON-resistance of the R-MOS is partially inherited while maintaining the high production yield and the high reliability of the DMOS.
In order to reduce the ON-resistance of the U-MOS to be equivalent to the R-MOS, it is necessary and indispensable to reduce the unit cell size a'. However, in the production method of the U-MOS shown in FIGS. 16 to 19 and FIG. 15, the reduction in the unit cell size a' is difficult. The reason thereof will be explained hereinafter.
At first, it will be explained in detail what determines the unit cell size of the U-MOS device.
In FIG. 15, the sizes of indicated portions have relations as follows. EQU a'=b'+2.alpha.' EQU b'=c'+2.beta.' EQU c'=d'+2.gamma.' (1) EQU d'=e'+2.delta.'
Wherein, a' is a unit cell size, b' is a distance between upper ends of two adjacent U-grooves, c' is a distance between adjacent gate electrodes, d' is a size of a contact hole, and e' is a size of a portion of the base contact layer 17 exposed to the surface. In addition, .alpha.' is a plane distance between the center and the upper end of the U-groove 50, .beta.' is a plane distance between the upper end of the U-groove 50 and the end of the gate electrode 9, .gamma.' is a plane distance between the end of the gate electrode 9 and the end of the contact hole, and .delta.' is a plane distance between the end of the contact hole and the end of the portion of the base contact layer 17 exposed to the surface.
In this case, in the present fine processing level, the adjustment accuracy of the mask is about 0.5 to 1 .mu.m, and also considering the size accuracy in the etching processing and the like, each value in the above-mentioned formulae (1) takes, for example, the following value. EQU .beta.'=1[.mu.m], .gamma.'=1.5[.mu.m], .delta.'=1[.mu.m], b'=8.5[.mu.m], c'=6.5[.mu.m], d'=3.5[.mu.m], e'=1.5[.mu.m] (2)
According to the formulae (1) and (2), the unit cell size a' is EQU a'=b'+2.alpha.'=8.5+2.alpha.'[.mu.m] (3)
wherein in order to reduce the unit cell size a', the value of the plane distance a' between the center and the upper end of the U-groove 50 is key.
According to FIGS. 16 to 18, it is understood that the size of .alpha.' is determined by the length of the bottom side and the processing accuracy of the U-groove 50, and the adjustment accuracy of the insulation film 26 (the mask for forming the U-groove) with respect to the p-type diffusion layer 23. FIG. 20 is a cross-sectional view of an important part including the U-groove 50 when a center line CL.sub.1 between the two adjacent p-type diffusion layers 23 overlaps a center line CL.sub.2 between the two adjacent insulation films 26, which corresponds to a case in which there is no mask deviation. In this case, a' is given by the following formula (4). EQU .alpha.'=.alpha.'1+.alpha.'2+.alpha.'3 (4)
However, .alpha.'1 is 1/2 of a length with which the bottom side portion of the U-groove 50 contacts with the n.sup.- -type drain layer 6, .alpha.'2 is a length with which the bottom side portion of the U-groove 50 contacts with the p-type base layer 16, and .alpha.'3 is a length of projection of the sidewall portion of the U-groove 50 onto the main surface of the wafer 21.
In this case, the right and left .alpha.'2s are approximately equal in FIG. 20. However, in fact, due to the presence of the deviation of the mask adjustment, the right and left .alpha.'2s are different, so that it is necessary that .alpha.'2 in each of the items in the formula (4) is set to be about 1.5 .mu.m. The reason thereof is that when mask adjustment of the insulation film 26 is worst, on account of the mask adjustment accuracy possible under the present circumstances, as shown in FIG. 21, with respect to the center line CL.sub.1 between the two adjacent p-type diffusion layers 23, the center line CL.sub.2 between the two adjacent insulation films 26 generates a positional deviation (for example, 1 .mu.m) in the right direction. In order to prevent an electric field concentration at the edge portion 12 so as to avoid the inconvenience resulting from a dielectric breakdown of the gate portion even when such positional deviation takes place, thus allowing the edge portion 12 at the groove bottom of the U-groove 50 not to be exposed to the n.sup.- -type drain layer 6 but to be positioned in the p-type base layer 16, it is necessary to make a design in which this positional deviation is taken into account. Therefore, the following formula (5) must be necessarily established with respect to lengths .alpha.'21 and .alpha.'22 with which the bottom side portions of the U-groove 50 contact with the p-type base layers 16. EQU 0&lt;.alpha.'21, .alpha.'22 (5)
In addition, with respect to .alpha.'1 and .alpha.'3, both of them are about 0.75 .mu.m in the present fine processing level, so that .alpha.' takes the following value according to the formula (4). EQU .alpha.'=0.75+1.5+0.75=3[.mu.m] (6)
Therefore, according to the formulae (3) and (6), the minimum value of the unit cell size a' is EQU a'=8.5+2.times.3=14.5[.mu.m] (7)
As described above, in the production method of the U-MOS shown in FIGS. 16 to 19 and FIG. 15, the reduction limit of the unit cell size a' is about 14.5 .mu.m, which is approximately the same as 15 .mu.m of the conventional DMOS type, and it has been difficult to significantly reduce the ON-resistance per area.